In recent years, the scaling of CMOS devices, such as the reduction of the gate length in MIS transistors or the thinning of gate insulating films, has allowed for improvements in operating speed and integration. In particular, MIS transistors having a gate insulating film with a thickness of 2 nm or less or a gate electrode with a gate length of about 50 nm have recently been developed.
FIG. 11 is a cross-sectional view of a conventional MIS transistor. As shown in the figure, this MIS transistor comprises an Si substrate 100 and a gate electrode 102 formed thereon via a gate insulating film 101 composed of silicon oxide. The gate electrode 102 is composed of polysilicon, and has oxide film sidewalls 103 formed on its side faces. The Si substrate 100 includes high-impurity-concentration source/drain regions 104 formed at the sides of the oxide sidewalls 103, and source/drain extension regions 106 formed in such a manner as to extend from the inner edges of the source/drain regions 104 toward the area under the gate electrode 102 and to sandwich a channel region 105.
According to the above MIS transistor, thinning the gate insulating film 101 allows for low-voltage operation and increases the current drive capability, however, it causes the following problems because the gate electrode 102 is composed of polysilicon.
(1) The impurity introduced into the gate electrode 102, such as boron, may penetrate the extremely thin oxide film 101 and may therefore enter the channel region 105, leading to deterioration in the electrical characteristics of the MIS transistor, such as fluctuations in threshold voltage.
(2) Thinning the gate insulating film 101 increases the capacitance of the film, causing a depletion layer to also be formed in the gate electrode 102 and increasing the substantial thickness of the gate insulating film 101. This problem is also attributed to the fact that there is a solid solubility limit for the impurity contained in the gate electrode 102, which is composed of polysilicon.
(3) There is an increase in the gate overlap capacitance, which is originated in the region Rgd where the source/drain extension region 106 and the gate electrode 102 overlap, as shown in FIG. 11. More specifically, as a result of thinning the gate insulating film 101 and reducing the gate length, the parasitic capacitance is increased by an amount that cannot be neglected. Such a significant increase in gate overlap capacitance is a factor that inhibits improvement in the operating speed of MIS transistors.
At present, the following suggestions have been proposed as solutions to the above problems.
(1) To prevent the penetration of boron, it has been suggested that an oxynitride film be used as a gate insulating film, due to its effectiveness in preventing impurity diffusion.
(2) As a measure for avoiding the depletion of the gate electrode, Publication No. 1 (W. C. Lee et al., “Investigation of Poly-Sil-xGex for Dual-Gate CMOS Technology”, IEEE Electron Device Lett., Vol. 19, 1998, p. 247), for example, suggests a CMOS device whose gate electrode contains polycrystalline SiGe, which allows for a high solid solubility for the impurity.
(3) As an approach to prevent the increase in gate overlap capacitance, Publication No. 2 (T. Ghani, et al., “100 nm Gate Length High Performance/Low Power CMOS Transistor Structure”, 1999 IEDM, p. 415), for example, suggests a notched-gate structure, in which the lower part of the polysilicon gate electrode is narrowed. In the notched-gate structure, the width of the upper part of the gate electrode is large, whereas the width of the lower part, which stipulates the transistor gate length, is small. This structure counteracts the possible increase in gate resistance caused by the reduction in gate length, thus reducing the increase in gate overlap capacitance.
The notched-gate structure is also described in, for example, Publication No. 3 (Japanese Unexamined Patent Publication No. 1987-45071). Publication No. 3 discloses a gate electrode which is composed of a polycrystalline silicon layer and a high-melting point metal silicide layer formed thereon. This gate electrode is heat-treated so that a thermally oxidized silicon film is grown on the side face of the gate electrode such that the thickness thereof is larger on the silicide layer, which is formed on top, than on the polycrystalline silicon layer, thus ultimately forming a notched-gate structure.
Further, Publication No. 4 (T. Skotnicki, et al., “Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS”, 2000 Symposium on VLST Technology, p. 156) reports a transistor in which the teachings of Publication Nos. 1 and 2 are combined, namely, in which a notched-gate structure is established by forming a gate electrode having a stacked structure composed of polycrystalline SiGe and polycrystalline Si and further by selectively dry-etching only the lower part of the gate electrode, which is composed of polycrystalline SiGe.
A notched-gate structure such as that disclosed in the above Publication No. 4 is relatively simple, yet effective in reducing the gate overlap capacitance, and is in this respect considered to be a promising approach.
However, the notched gate cited in Publication No. 4, while being simple in structure, requires a special dry etching technique by which only the lower part of the gate electrode, which is composed of polycrystalline SiGe, can be selectively etched in the lateral direction, and thus entails a complicated manufacturing process.
In addition, Japanese Unexamined Patent Publication No. 1994-196495 (U.S. Pat. No. 5,512,771) teaches, in FIG. 2 and its description, giving the gate electrode a convex shape in sectional view to thereby reduce the gate-to-drain overlap capacitance.
An object of the present invention is to provide a semiconductor device with an MIS transistor structure and a process for manufacturing the same in which a notched-gate structure is formed by selectively narrowing the lower gate electrode element using a simple process.